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[Applications] manchester

Description: 用verilog HDL实现曼彻斯特编码的源码-with Manchester Verilog HDL source code
Platform: | Size: 4131 | Author: 刘波 | Hits:

[Communication-Mobile] 曼彻斯特编解码Verilog代码

Description: 曼彻斯特编解码Verilog代码 .zip-Manchester codec Verilog code. Zip
Platform: | Size: 10042 | Author: 崔广辉 | Hits:

[Applications] manchester

Description: 用verilog HDL实现曼彻斯特编码的源码-with Manchester Verilog HDL source code
Platform: | Size: 4096 | Author: 刘波 | Hits:

[Communication-Mobile] 曼彻斯特编解码Verilog代码

Description: 曼彻斯特编解码Verilog代码 .zip-Manchester codec Verilog code. Zip
Platform: | Size: 10240 | Author: 崔广辉 | Hits:

[VHDL-FPGA-Verilog] manchester_verilog

Description: 这时manchesite编码，VERILOG语言，VHDL的找本站我发的帖子-manchesite time coding, VERILOG language, VHDL I find a site in a posting
Platform: | Size: 9216 | Author: 李无志 | Hits:

[VHDL-FPGA-Verilog] 用cpld实现曼彻斯特编码

Description: 用cpld实现曼彻斯特编码 用verilog HDL进行曼彻斯特编码，用于通信中-cpld achieve with Manchester encoding with Verilog HDL Manchester encoding. for Communication
Platform: | Size: 4096 | Author: 李鹏 | Hits:

[VHDL-FPGA-Verilog] man_Verilog

Description: 曼彻斯特编解码，是Verilog语言代码，不多介绍了，用途非常广泛了-Manchester encoding and decoding is the Verilog language code, introduced a few, a very extensive use
Platform: | Size: 9216 | Author: 刘超 | Hits:

[VHDL-FPGA-Verilog] NRZ_2_Manchester

Description: NRZ码到Manchester转换器 verilog-NRZ code to Verilog converter Manchester
Platform: | Size: 1024 | Author: leysion | Hits:

[VHDL-FPGA-Verilog] mancheester_v

Description: 用Verilog HDL实现的曼彻斯特编码器和解码器。-Using Verilog HDL realize the Manchester encoder and decoder.
Platform: | Size: 9216 | Author: wangyunshann | Hits:

[VHDL-FPGA-Verilog] manchester_verilog

Description: 曼彻斯特编解码Verilog代码 非常好的 速度快，而且资源占用少。 -Manchester codec Verilog code very good speed, but also occupy less resources.
Platform: | Size: 10240 | Author: 王鹏 | Hits:

[VHDL-FPGA-Verilog] mcst

Description: 曼彻斯特编码实现，verilog HDL 做的，我也是从网上下的-Manchester encoding to achieve, verilog HDL to do, I am also from the Internet under
Platform: | Size: 1024 | Author: yy | Hits:

[MiddleWare] DifferentialManchestercodedecodingverilogcode

Description: 差分曼彻斯特码解码的verilog代码 -Differential Manchester code decoding verilog code
Platform: | Size: 1024 | Author: 徐龙 | Hits:

[VHDL-FPGA-Verilog] manchester_verilog

Description: 用verilog写的一个manchester code的代码，含编解码-Used to write a verilog code for manchester code containing codec
Platform: | Size: 9216 | Author: stream | Hits:

[VHDL-FPGA-Verilog] Manchester

Description: 曼彻斯特编解码源代码,还包含曼彻斯特码的说明文档-Manchester Encoder-Decoder
Platform: | Size: 40960 | Author: cst008 | Hits:

[VHDL-FPGA-Verilog] manchesterbyxilinx

Description: 曼彻斯特编解码的实现（Verilog）,包含有测试文件。-manchester encode and decode with verilog，Test File is included。
Platform: | Size: 10240 | Author: cheuna | Hits:

[VHDL-FPGA-Verilog] Manchester

Description: manchester coding verilog
Platform: | Size: 9216 | Author: Jacknapes | Hits:

[VHDL-FPGA-Verilog] manchester

Description: verilog 实现manchester编解码，最高速率5mhz-verilog manchester code to achieve the highest rate of 5mhz
Platform: | Size: 4096 | Author: 王红星 | Hits:

[VHDL-FPGA-Verilog] mach_test_ok

Description: verilog曼切斯特编码解码的FPGA实现-verilog Manchester encoding and decoding on FPGA
Platform: | Size: 2048 | Author: 朱 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 曼彻斯特编码的verilog实现,复制到quartus II可用-Manchester verilog realize the code,Copy to quartus II available
Platform: | Size: 10240 | Author: 尹晋文 | Hits:

[VHDL-FPGA-Verilog] Manchester-Encoding-Verilog

Description: THIS DESIGN IS PROVIDED TO YOU “AS IS”. XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE. This design has not been verified on hardware (as opposed to simulations), and it should be used only as an example design, not as a fully functional core. XILINX does not warrant the performance, functionality, or operation of this Design will meet your requirements, or that the operation of the Design will be uninterrupted or error free, or that defects in the Design will be corrected. Furthermore, XILINX does not warrant or make any representations regarding use or the results of the use of the Design in terms of correctness, accuracy, reliability or otherwise. -THIS DESIGN IS PROVIDED TO YOU “AS IS”. XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE. This design has not been verified on hardware (as opposed to simulations), and it should be used only as an example design, not as a fully functional core. XILINX does not warrant the performance, functionality, or operation of this Design will meet your requirements, or that the operation of the Design will be uninterrupted or error free, or that defects in the Design will be corrected. Furthermore, XILINX does not warrant or make any representations regarding use or the results of the use of the Design in terms of correctness, accuracy, reliability or otherwise.
Platform: | Size: 8192 | Author: liyapei | Hits:
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